Monolithic growth of epitaxial silicon devices via co-doping
US20260032936A1
Abstract
In one general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant, where the first type of electrically active dopant of the first layer is one of either a P-type or an N-type and the second type of electrically active dopant of the second layer is the other one of either the P-type or N-type.
Description (excerpt)
RELATED APPLICATION This application is a divisional of U.S. patent application Ser. No. 17/967,754, filed Oct. 17, 2022, which claims priority to U.S. Provisional Patent Appl. No. 63/257,006, filed Oct. 18, 2021, which are all herein incorporated by reference. This invention was made with Government support under Contract No. DE-AC52-07NA27344 awarded by the United States Department of Energy. The Government has certain rights in the invention. FIELD OF THE INVENTION The present invention relates to semiconductor devices such as diodes, and more particularly, this invention relates to silicon devices having co-doped layers, thereby providing sharp, narrow junctions. BACKGROUND Among the great challenges of materials science is discovering a material that satisfies conflicting requirements and also possesses specific properties for a particular application. This is especially true when attempting to create complex electronic components where different materials interface with each other. Such interface should provide a desired result, or conversely, should not adversely affect the electronic component. Consider stacked diodes, for example. A diode is a two-terminal electronic component that conducts current primarily in one direction. A diode has low resistance in one direction, and high resistance in the other. A semiconductor junction diode is typically made of a crystal of semiconductor, usually silicon. Impurities are added to create a region on one side that includes negative charge carriers, called an N-type semiconductor. A region on the other side that includes positive charge carriers is called a P-type semiconductor. The boundary between these two regions is called a P-N junction where a depletion region is formed having a depletion width. When a sufficiently higher electrical potential is applied to the P side (the anode) than to the N side (the cathode), the potential allows electrons to flow through the depletion region from the N-type side to the P-type side. Growth of low voltage monolithic tunnel and Zener diodes via epitaxy is challenging. Sharp junctions with highly degenerate doping on both sides is required for all tunneling diodes and Zener diodes with a low Zener voltage. At elevated temperatures, the doped regions tend to diffuse into each other, reducing the abrupt changes from p-type to n-type and reducing the degeneracy. This in turn prevents fabrication of stacked structures. The ability to epitaxially grow these structures would be desirable because it would enable fabrication of complex multilayer stacks. However, the diffusion problem has heretofore prevented successful implementation of structures having such multilayer stacks, especially via high temperature epitaxial growth. BRIEF SUMMARY A process, in accordance with one embodiment, includes growing a first layer having a first type of electrically active dopant. A second layer having a second type of electrically active dopant is also grown, thereby forming a first diode. The first type of electrically active dopant of the first layer is one of either a P-type or an N-type and the second type of electrically active dopant of the second layer is the other one of either the P-type or N-type. The growing steps are repeated at least one time for forming at least one additional diode above the first diode. Other aspects and advantages of the present invention will become apparent from the following detailed description, which, when taken in conjunction with the drawings, illustrate by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is flowchart depicting a process for producing a plurality of multi-layer diodes, in accordance with an exemplary embodiment. FIG. 2 is flowchart depicting a process for producing a plurality of multi-layer diodes, in accordance with an exemplary embodiment. FIG. 3 is a drawing of an exemplary structure of a stack of diodes, in accordance with one embodiment. FIG. 4 is an exemplary band diagram of a stack of diodes, in accordance with one embodiment. FIG. 5 is a drawing of an exemplary
Filing details
- Inventors
- Caitlin Anne Chapin
- Assignee
- The United States Of America As Represented By The Secretary Of The Army
- Filed
- Apr 17, 2025
- Granted
- Application pending
Bibliographic data and excerpted text sourced from Google Patents (public record) as part of IP TechMatch's current-filings monitor. This filing is not part of the 2019 historical archive. For the authoritative full text, drawings, and legal status, see the source links above or consult USPTO records directly.