Neural network based prediction of semiconductor device response
US20260165090A1
Abstract
A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.
Description (excerpt)
CROSS-REFERENCE This Application is a continuation of U.S. Nonprovisional patent application Ser. No. 18/052,654, filed Nov. 4, 2022; which claims priority to U.S. Provisional Patent Application No. 63/281,106, filed on Nov. 19, 2021; both of which and all references cited herein are hereby incorporated by reference herein in their entirety into this disclosure. FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT The United States Government has ownership rights in this invention. Licensing inquiries may be directed to Office of Technology Transfer, US Naval Research Laboratory, Code 1004, Washington, DC 20375, USA; +1.202.767.7230; techtran@nrl.navy.mil, referencing Navy Case #210892. TECHNICAL FIELD The present disclosure relates to evaluation of a semiconductor device, particularly to a method for predicting the electrical response of a semiconductor device prior to device fabrication based on characterization or measurements of the semiconductor wafer on which the device is to be fabricated, combined with a properly designed machine learning model trained on characterization and measurement data of similar wafers and the devices fabricated on the these wafers. BACKGROUND Modern semiconductor fabrication employs dozens of steps including boule growth, sawing, polishing, epitaxy, implant, and lithography. However, these process steps can produce defects that are deleterious to device performance and/or reduce device yield from a wafer experiencing these defects. One common defect in semiconductor wafers stems from the presence of particles that may be deposited or the wafer surface, even in clean-room facilities used in modern semiconductor manufacturing. Similarly, process steps such as etching and deposition can produce distinct particulates within the wafer material that alter the electrical response of the completed device. The presence of these particles can be identified by visual inspection or by pre-defined computational image analysis using optical, electron micrograph, or related imaging techniques. Other process steps such as epitaxy or dopant implantation can produce defects in the wafer that can be readily identified via photoluminescence, electroluminescence, cathodoluminescence, Auger spectroscopy, or similar techniques that probe the radiative or non-radiative transitions of the defect. Again, these types of defects are easily identified by one skilled in the art through analysis of metrology images or, similarly, by analysis of pre-determined shapes found via a computer algorithm, which itself is based on features classified by an expert. Semiconductor manufacturing employs a multitude of data science algorithms for process analysis, process control, process optimization, and general yield improvement. A rich set of data is generated by the process parameters of the fabrication tools used as well as from in-situ measurements by the tools themselves. A suite of data science analysis tools has long been applied to find correlations in process and test data for process optimization and general yield analysis. For example, it is known from statistical analysis utilizing a specific workflow (e.g., specific selections of wafer position in the various deposition systems coupled to die position on that specific wafer during lithography and etch steps) predictably correlates to produce devices with improved metrics, e.g., maximum operating frequency. Additionally, metallized test structures are commonly incorporated, typically at the later stages of fabrication, to provide electrical test data during the or post process. It is common to use the electrical response of the final device or test structures on the wafer as one parameter for statistical analysis of the overall fabrication process. One example is correlation analysis to relate process parameters or metrology metrics at various stages of processing to the electrical response of the final device. Evaluation of wafers before devices have been fabricated is essential to maximize yield and reduce the incidence of defective devices. See U.S. Pat. No. 11,415,518 to Anderson et al., “Mapping and Evaluating GaN Wafers for Vertical Device Applications.” This evaluation general framework can be used to identify features that, within a statistical likelihood, will result in reduced yield per process step or in the overall process flow. Optical metrology is one evaluation method that can be performed to inspect the semiconductor surface before or after a particular process step. See U.S. Patent Application Publication No. 2021/0389126 to Gallagher et al., entitled, “Surface Profile Mapping for Evaluating III-N Device Performance and Yield.” After devices have been processed on a wafer, such metrology can be employed to trace back and identify specific features or defects that produced a failed device at that physica
Filing details
- Inventors
- Michael A. Mastro
- Assignee
- The Government Of The United States Of America, As Represented By The Secretary …
- Filed
- Dec 30, 2025
- Granted
- Application pending
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