In-memory acceleration using 6t-rrams with signed weight values

Description (excerpt)

RIGHTS OF THE GOVERNMENT The invention described herein may be manufactured and used by or for the Government of the United States for all governmental purposes without the payment of any royalty. Pursuant to 37 C.F.R. § 1.78(a)(4), this application claims the benefit of and priority to prior filed co-pending Provisional Application Ser. No. 63/758,001, filed Feb. 13, 2025, which is expressly incorporated herein by reference in its entirety. FIELD OF THE INVENTION The present invention relates generally to compute-in-memory devices and, more particularly, to compute-in-memory devices having multiple transistors and one resistive random access memory. BACKGROUND OF THE INVENTION Traditional machine-learning hardware separates memory and computation into distinct physical blocks (e.g., “von Neumann architectures”). Neural-network weights may be stored in conventional memory arrays while multiply-accumulate operations are executed in separate digital logic units. This separation forces data to shuttle repeatedly between memory and processor, introducing potential errors and inefficiencies (e.g., “memory wall bottleneck,” etc.) As neural networks increase in size and complexity, the energy and latency associated with weight fetching dominate total system cost. Further, multi-bit weight storage often requires two or more memory cells per synapse, and storing positive and negative values normally requires paired devices or elaborate digital encoding schemes. These constraints have made it increasingly difficult to scale deep-learning systems in an energy-efficient manner, particularly in edge-computing environments with tight area and power budgets. Compute-in-memory (CIM) architectures attempt to alleviate these challenges by performing at least part of the computation within the memory array itself. Resistive-RAM (RRAM) devices are especially attractive for CIM because their analog conductance states naturally support multiply-accumulate operations. However, existing RRAM CIM designs have struggled to provide compact support for signed (+/−) weights, requiring two 1T1R devices per synapse (one positive, one negative) or additional digital circuitry that increases area and degrades array efficiency. Accordingly, there may be a need for improved RRAM-based CIM cells. SUMMARY OF THE INVENTION The present invention overcomes the foregoing problems and other shortcomings, drawbacks, and challenges of current electronic circuits for assigning synaptic weights. While the invention will be described in connection with certain embodiments, it will be understood that the invention is not limited to these embodiments. To the contrary, this invention includes all alternatives, modifications, and equivalents as may be included within the spirit and scope of the present invention. According to one embodiment of the present invention a memristive circuit includes a signal source; a bit line; and a six-transistor, one-resistive random-access memory (6T1R) cell including: a resistive random-access memory (RRAM) element having a first terminal and a second terminal, the second terminal being electrically coupled to the bit line; a positive-weight conduction loop including: a first transistor (M 1 ) having a gate configured to receive a positive-state gate voltage (V p ), a source coupled to the signal source, and a drain configured to control a state of a logic inverter, the first transistor is configured to selectively pass the signal source to the logic inverter; the logic inverter, comprising a third transistor (M 3 ) and a fourth transistor (M 4 ), each having gates coupled to the drain of M 1 , the logic inverter having an output; and a fifth transistor (M 5 ) having a gate coupled to the output of the logic inverter, a source coupled to a training supply voltage (VDD), and a drain coupled to the first terminal of the RRAM element; and a negative-weight conduction loop including a second transistor (M 2 ) having a source coupled to the signal source and a gate configured to receive a negative-state gate voltage (V n ); and a sixth transistor (M 6 ) having a gate coupled to a drain of the second transistor, a drain coupled to the first terminal of the RRAM element, and a source coupled to ground. The RRAM element is configured to store a plurality of resistance states corresponding to magnitudes of synaptic weights, a sign and magnitude of the synaptic weight being determined by a direction and a magnitude of current conducted through the RRAM element via one of the positive-weight conduction loop and the negative-weight conduction loop; and during a read operation, the resistance state of the RRAM element modulates a current on the bit line, a magnitude of the current thereby representing the magnitude of the synaptic weight. According to another embodiment of the present disclosure, an array of memristive circuit cells